`timescale 1ns/1ps

module pll_tb();
	
	reg areset;
	reg inclk0;
	wire c0;
	wire locked;
	
	
	pll pll_instanc0(
		.areset(areset),
		.inclk0(inclk0),
		.c0(c0),
		.locked(locked)
	);
	
	initial inclk0 = 1;
	always #10 inclk0=~inclk0;
	initial begin
		areset = 0;
		#201;
		areset = 1;
		#2000;
		$stop;
	end

endmodule
